1. Field of the Invention
The present invention relates to a semiconductor device suitable for an SOI-type semiconductor device, and more particularly to an improvement to suppress a leak current during standby and a circuit delay during operation.
2. Description of the Background Art
In the present specification, the term xe2x80x9cMOS transistor (MOSFET)xe2x80x9d broadly includes an insulated gate transistor whose gate electrode is made of a conductive material other than metal as well as made of metal in accordance with the conventional practice in this field. Further, an insulated gate semiconductor element comprising another electrode interposed between a control electrode and a channel region such as a memory element of flash EEPROM is also referred to as a MOS transistor.
For achieving a system LSI, it is known that it is more advantageous in degree of integration, operating speed and power consumption to form a CMOS transistor (complementary MOS transistor: CMOSFET) which is a constituent element of an LSI in a main surface of an SOI (Silicon On Insulator) substrate than in a main surface of a bulk-type semiconductor substrate. FIG. 20 is a cross section schematically showing a structure of an SOI substrate. In an SOI substrate 100, a buried oxide layer (BOX layer) 114 made of a silicon oxide is formed on a supporting substrate 113 which is a semiconductor substrate mainly made of a silicon and an SOI layer 115 made of a crystalline silicon is formed further thereon.
The BOX layer 114 has a thickness of about 0.01 xcexcm to 0.4 xcexcm and the SOI layer 115 has a thickness of about 0.1 xcexcm to 1 xcexcm. MOS transistors are formed in a main surface of the SOI layer 115. The MOS transistors are isolated from one another by LOCOS or STI (Shallow Trench Isolation). A channel region in an active region of the MOS transistor is also referred to as a body region.
The semiconductor device having an SOI structure constituted of the supporting substrate 113, the BOX layer 114 and the SOI layer 115, in which the active region is surrounded by the BOX layer 114 and an isolation insulating film 150 (hereinafter, referred to as xe2x80x9cfull isolationxe2x80x9d or xe2x80x9cFull STI: Full Shallow Trench Isolationxe2x80x9d and abbreviated to xe2x80x9cFTIxe2x80x9d) whose bottom surface reaches the BOX layer 114, has an advantage that no latch up occurs even if the CMOS transistor is formed in the SOI layer 115. Further, since source/drain regions of the MOS transistor are in contact with the BOX layer 114, obtained is an advantage that junction capacitance becomes smaller, high-speed operation is available, a leak current during standby becomes smaller and power consumption is reduced as compared with a semiconductor device in which the MOS transistors are formed directly in the main surface of the semiconductor substrate.
When the SOI layer 115 which is a semiconductor layer formed on the BOX layer 114 has a thickness not less than e.g., 0.15 xcexcm, however, carriers (positive hole in an NMOS transistor and electrons in a PMOS transistor) generated by impact ionization phenomenon are accumulated immediately below the channel region. This raises problems that kink appears in the Ids-Vds characteristic of a transistor and that an operating breakdown voltage is deteriorated. Further, since there are various problems caused by a floating-substrate effect such as frequency dependency appearing in the delay time due to an unstable potential of the channel region, the potential of the channel region is normally fixed. The semiconductor device in which the potential of the channel region is fixed as above is disclosed in Japanese Patent Application Laid Open No. 58-124243 (1983).
Recently has been made an attempt that an isolation insulating film 116 (hereinafter, xe2x80x9cpartial isolationxe2x80x9d or xe2x80x9cPartial STI: Partial Shallow Trench Isolationxe2x80x9d and abbreviated to xe2x80x9cPTIxe2x80x9d) whose bottom surface does not reach the BOX layer 114 is used for isolation so as to collectively fix the potentials of the channel regions of a plurality of transistors of the same conductivity type, instead of individually fixing the potentials of the channel regions of MOS transistors, thereby promoting miniaturization. The semiconductor device having this structure is disclosed in IEEE international SOI Conference, October (1997) and the like.
FIG. 21 is a plan view showing a semiconductor device in the background art. In the semiconductor device, an NMOS region and a PMOS region are formed in the SOI layer, and a plurality of NMOS transistors are formed in the NMOS region and a plurality of PMOS transistors are formed in the PMOS region. An active region 102 of each MOS transistor is formed and a pair of source/drain regions 103 and 104 are formed with a channel region interposed therebetween in the active region 102. One of the source/drain regions 103 and 104 is a source region and the other is a drain region, both of which serve as a source of carriers (electrons or positive holes) or have a function of draining the carriers out, and each of them is referred to as xe2x80x9ca source/drain regionxe2x80x9d in the present specification.
A body contact region 112 is formed in each of the NMOS region and the PMOS region. The body contact region 112 and the active region 102 of each MOS transistor are isolated from each other by a PTI 101 serving as an isolation region. The body contact region 112 is provided to fix the potential of the channel regions (body regions) of a plurality of MOS transistors of the same conductivity type.
Source/drain lines 105 and 107 are connected to the source/drain regions 103 and 104, respectively. Further, a gate electrode (gate line) 106 is provided above the channel region. The gate electrode 106 is connected to a metal wire 110 through a gate electrode contact 109. A metal wire 111 is connected to the contact region 112. An isolation width 108 refers to the width of the PTI 116 which isolates the NMOS region and the PMOS region.
FIG. 22 is a cross section taken along the line Axe2x80x94A off FIG. 21. A pair of source/drain regions 103 and 104 are selectively formed with an N-type channel region 122p or a P-type channel region 122n interposed therebetween in each of the active regions 102 formed in the SOI layer 115. A high-concentration source/drain region 124 and a low-concentration source/drain region 123 are formed in each of the source/drain regions 103 and 104. The PTI 116 isolating two adjacent active regions 102 does not reach the BOX layer 114 and a P-type channel stopper 125 and an N-type channel stopper 126 are formed immediately below the PTI 116.
A gate insulating film 117 is formed on the channel regions 122p and 122n and the gate electrode 106 having a double-layered structure consisting of a doped polysilicon layer 118 and a metal layer 119 is formed on the gate insulating film 117. Specifically, the gate electrode 106 is opposed to the channel regions 122p and 122n with the gate insulating film 117 interposed therebetween. The gate electrode 106 is covered with an insulating film 120 and a sidewall 121 is formed on a side surface of the gate electrode 106 with the insulating film 120 interposed therebetween. The source/drain lines 105 and 107 are connected to the source/drain regions 103 and 104 through contact plugs 131 and 129 penetrating interlayer insulating films 127 and 128.
The parasitic capacitance of the source/drain region 103 or 104 of the MOS transistor is generated by junction between the same and the channel region 122p or 122n and that between the same and the channel stopper 125 or 126. To improve the operating speed of the MOS transistor, it is desirable that the parasitic capacitance should be small.
The leak current of the MOS transistor during standby is caused by a generated current flowing in a depletion layer created by application of reverse bias to a junction formed between the source/drain regions 103 and 104 and the channel regions 122p and 122n or that between the source/drain regions 103 and 104 and the channel stoppers 125 and 126. Further, the generated current is generated also when the reverse bias is applied to the junction formed between the channel stoppers 125 and 126. This current also contributes to the leak current. If the leak current during standby is large, the power consumption of the whole semiconductor chip increases. Therefore, it is desirable that the leak current during standby should be small.
FIG. 23 is a cross section of the PMOS region taken along the line Bxe2x80x94B of FIG. 21. The gate electrode 106 is connected to the metal wire 110 through the contact plug 109 penetrating the interlayer insulating film 127. Further, the body contact region 112 is connected to the metal wire 111 through the contact plug 135 penetrating the interlayer insulating film 127. Furthermore, the body contact region 112 containing an N-type impurity of high concentration is connected to the N-type channel region 122p through the N-type channel stopper 126.
Though not shown, in the NMOS region, the body contact region 112 containing a P-type impurity of high concentration is connected to the P-type channel region 122n through the P-type channel stopper 125. Therefore, by supplying the metal wire 111 with a bias potential individually in the PMOS region and the NMOS region, it is possible to fix the channel regions 122p and 122n to the bias potential.
In the semiconductor device in which a plurality of MOS transistors formed in the SOI substrate 100 are isolated from one another by the PTI 116, however, since the leak current during standby flows through the channel stopper immediately below the PTI 116, there arises a problem that the power consumption during standby becomes larger as compared with that in the semiconductor device using the FTI 150 as an isolation. Further, during operation, there are problems that a substrate current is generated by electric charges accumulated in the channel region (body region) 122 and there may be a case, depending on the operating frequency, where noise is superimposed on a circuit signal and a circuit operation becomes slower due to variation in threshold voltage caused by the substrate current.
An object of the present invention is to provide a semiconductor device capable of suppressing the leak current during standby and the circuit delay during operation.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: at least one MOS transistor formed in a main surface of a semiconductor substrate, being a constituent element of a circuit operating in synchronization with a system clock; and a body bias generation circuit for applying a body potential to a body region of the at least one MOS transistor at a different level including a potential of reverse bias relative to a source region in response to a signal of the circuit operating in synchronization with the system clock.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the body bias generation circuit selectively applies one of the potential of reverse bias and a potential of zero bias relative to the source region to the body region as the body potential.
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the body bias generation circuit selectively supplies the body region with one of M (Mxe2x89xa72) supply currents of different magnitudes.
According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the body bias generation circuit comprises M oscillator circuits for generating M clocks having different frequencies; and M charge pump circuits for intermittently supplying the body region with currents individually in synchronization with the M clocks.
According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the body bias generation circuit comprises a monitor circuit for comparing a difference between a potential of the body region and that of the source region with a reference value and outputting a comparison result, and one of the M oscillator circuits which generates a clock having the highest frequency so operates in response to the comparison result as to generate the clock when the difference is smaller than the reference value.
According to a sixth aspect of the present invention, in the semiconductor device according to the fourth or fifth aspect, at least one of the M clocks has a frequency higher than that of the system clock.
According to a seventh aspect of the present invention, in the semiconductor device according to any one of the fourth to sixth aspects, the circuit operating in synchronization with the system clock is a dynamic RAM, and one of the M oscillator circuits which generates a clock having the lowest frequency comprises a battery backup mode control circuit which judges whether an operating mode of the dynamic RAM is a normal operation mode or a battery backup mode, and generates the clock when it is judged that the operating mode is the normal operation mode and generates the clock only during a refresh request when it is judged that the operating mode is the battery backup mode.
According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, the semiconductor substrate is an SOI substrate, the at least one MOS transistor includes a plurality of MOS transistors of the same conductivity type isolated from one another by partial isolation, the SOI substrate has a channel stopper doped with an impurity immediately below the partial isolation, and the body bias generation circuit supplies the body potential in common to the plurality of MOS transistors through the channel stopper.
According to a ninth aspect of the present invention, in the semiconductor device according to the eighth aspect, the at least one MOS transistor further includes another MOS transistor which is different in conductivity type from the plurality of MOS transistors, and the another MOS transistor and at least one of the plurality of MOS transistors adjacent thereto are isolated from each other by full isolation.
According to a tenth aspect of the present invention, in the semiconductor device according to any one of the first to ninth aspects, the semiconductor substrate is an SOI substrate, the at least one MOS transistor includes M (Mxe2x89xa72) MOS transistors, the M MOS transistors are arranged, being divided into N (2xe2x89xa6N less than M) function blocks, and the body bias generation circuit is divided into L (2xe2x89xa6Lxe2x89xa6N) unit body bias generation circuits and the L unit body bias generation circuits individually supply body regions of MOS transistors belonging to L groups selected among the N function blocks with the body potential of reverse bias.
According to an eleventh aspect of the present invention, in the semiconductor device according to the tenth aspect, at least two function blocks which are adjacent to each other among the N function blocks are isolated from each other by full isolation.
According to a twelfth aspect of the present invention, in the semiconductor device according to any one of the first to eleventh aspects, the semiconductor substrate is an SOI substrate, the body bias generation circuit is formed in the main surface, and the body bias generation circuit and the at least one MOS transistor is isolated from each other by full isolation.
According to a thirteenth aspect of the present invention, in the semiconductor device according to any one of the first to twelfth aspects, the semiconductor substrate is an SOI substrate, and the SOI substrate has a bottom layer which is positioned immediately below the at least one MOS transistor, being in contact with a surface on the opposite side of the main surface of a buried insulating film and is a semiconductor layer in which an impurity is introduced.
According to a fourteenth aspect of the present invention, the semiconductor device according to the thirteenth aspect further comprises: a bottom potential generation circuit for selectively applying a potential of reverse bias relative to a source region of a MOS transistor positioned immediately above the bottom layer to the bottom layer.
According to a fifteenth aspect of the present invention, in the semiconductor device according to the fourteenth aspect, the bottom potential generation circuit selectively applies one of the potential of reverse bias and the same potential as that of the source region of the MOS transistor positioned immediately above the bottom layer to the bottom layer.
According to a sixteenth aspect of the present invention, in the semiconductor device according to the fourteenth or fifteenth aspect, the bottom potential generation circuit applies the potential in synchronization with the body bias generation circuit.
According to a seventeenth aspect of the present invention, in the semiconductor device according to the thirteenth aspect, the body bias generation circuit supplies the bottom layer with a potential supplied to the body region at the same time.
In the device of the first aspect of the present invention, since the body bias generation circuit for selectively applying the body potential of reverse bias to the body region, it is possible to apply the reverse bias to the body region when the circuit including the MOS transistors is in the standby mode. That reduces the leak current during standby and achieves the semiconductor device of less current consumption.
In the device of the second aspect of the present invention, since the body bias generation circuit can selectively apply not only reverse bias but also zero bias, it is possible to operate the circuit including the MOS transistors with its body potential fixed to zero bias.
In the device of the third aspect of the present invention, the body bias generation circuit can selectively supply the body region with one of supply currents of a plurality of levels, a suitable supply current can be supplied in accordance with the magnitude of the body current flowing the MOS transistor. That makes it possible to effectively suppress accumulation of electric charges in the body region while suppressing the current consumption, and the problem of variation in threshold voltage and delay of the circuit operation can be solved.
In the device of the fourth aspect of the present invention, the body bias generation circuit for supplying a plurality of supply currents can be easily constituted of M oscillator circuits having different clock frequencies and M charge pump circuits operating individually in synchronization with the M oscillator circuits.
In the device of the fifth aspect of the present invention, since the monitor circuit is provided, it is possible to automatically supply a suitable supply current in accordance with the magnitude of the body current without inputting the control signal from the outside.
In the device of the sixth aspect of the present invention, since the oscillator circuit for generating a clock which is higher in frequency than the system clock, it is possible to remove an influence on the operation of the MOS transistor due to accumulation of the electric charges in the body region.
In the device of the seventh aspect of the present invention, since a clock of low frequency is generated only during the period while the MOS transistor operates, that is, the refresh is requested when the dynamic RAM operates in the battery backup mode by the function of the battery backup mode control circuit, it is possible to further reduce the current consumption.
In the device of the eighth aspect of the present invention, it is possible to supply the body potential to a plurality of MOS transistors through the channel stopper.
In the device of the ninth aspect of the present invention, since there is some pair of MOS transistors which are isolated from each other by full isolation among pairs of MOS transistors of different conductivity types, it is possible to further suppress the leak current.
In the device of the tenth aspect of the present invention, since the each function block or each group of function blocks is attended by the body bias generation circuit, it is possible to optimize the body potential in accordance with the operation of each function block or each group of function blocks, and the power consumption of the whole semiconductor device can be further effectively reduced.
In the device of the eleventh aspect of the present invention, since there is a pair of adjacent function blocks which are isolated from each other by full isolation among the function blocks, it is possible to further suppress the leak current.
In the device of the twelfth aspect of the present invention, since the semiconductor substrate is an SOI substrate and the body bias generation circuit and the MOS transistor which is to be supplied thereby with the body potential are isolated from each other by full isolation, it is possible to further suppress the leak current.
In the device of the thirteenth aspect of the present invention, since the bottom layer is provided, it is possible to further suppress the leak current by fixing the potential of the bottom layer.
In the device of the fourteenth aspect of the present invention, since the bottom potential generation circuit is provided, it is possible to further suppress the leak current by changing the potential of the bottom layer in synchronization with the body potential.
In the device of the fifteenth aspect of the present invention, since the bottom potential generation circuit selectively applies the same potential as that of the source region of the MOS transistor positioned immediately above the bottom layer to the bottom layer, it is possible to operate the circuit including the MOS transistors with the potential of the supporting substrate fixed to zero bias.
In the device of the sixteenth aspect of the present invention, since the bottom potential generation circuit applies the potential in synchronization with the body bias generation circuit, it is possible to further suppress the leak current.
In the device of the seventeenth aspect of the present invention, since the body bias generation circuit has the function of the bottom potential generation circuit, it is possible to simplify the circuit constitution and reduce the area of the semiconductor chip.
As a document disclosing the technique relevant to the present invention, known is Japanese Patent Application Laid Open Gazette No. 11-340465 (hereinafter, referred to as document 1).
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.